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Title company name (assignee) Country/Patent Coverage filing/creation date grant date id inventor/author priority date publication date representative figure link result link
Partition matrices into sub-matrices that include nonzero elements US US-20200133994-A1 S Chatterjee, C Ghosh, M Parthasarathy
Storing neural networks and weights for neural networks US US-20200134443-A1 M Qin
End-to-end quality of service in edge computing environments US US-20200136920-A1 KA Doshi, NM Smith, FG Bernat, T Verrall, R Gadiyar
DETECTION, TRACKING AND RECOGNITION ON NETWORKS OF DIGITAL NEUROSYNAPTIC CORES US US-20200134843 A Andreopoulos, A Amir, TK Nayak
DYNAMIC ADAPTATION OF DEEP NEURAL NETWORKS US US-20200134461 SM Chai, A Nadamuni Raghavan, S Parajuli
Alignment Techniques to Match Symmetry Point as Zero-Weight Point in Analog Crosspoint Arrays US US-20200117699 S Kim, H Kim, T Gokmen, M Rasch
EFFICIENT PROCESSING OF CONVOLUTIONAL NEURAL NETWORK LAYERS USING ANALOG-MEMORY-BASED HARDWARE US US-20200117986 G Burr, B Killeen
Optoelectronic Computing Systems US US-20200110992 A Hosseinzadeh, Y Xu, Y Bai, H Meng, R Gagnon, C Lu
MANY TASK COMPUTING WITH MESSAGE PASSING INTERFACE US US-20200110589 HGV Bequet, RE Stogner, C Zhang, EJ Yang, Q Gong
FAULT-TOLERANT POWER-DRIVEN SYNTHESIS US US-20200097833 CJ Alpert, P Datta, MD Flickner, Z Li, DS Modha
SYSTEM AND METHOD FOR USING A DEEP LEARNING NETWORK OVER TIME US US-20200104704 R Venkataramani, SH Anamandra, H Ravishankar
THERMODYNAMIC RAM TECHNOLOGY STACK US US-20200110999 A Nugent, T Molter
EXPLOITING ACTIVATION SPARSITY IN DEEP NEURAL NETWORKS US US-20200104692 R Hill, A Lamb, M Goldfarb, A Ansari, C Lott
LOW SPIKE COUNT RING BUFFER MECHANISM ON NEUROMORPHIC HARDWARE US US-20200097801 A Andreopoulos
AUTOMATED EXCHANGES OF JOB FLOW OBJECTS BETWEEN FEDERATED AREA AND EXTERNAL STORAGE SPACE US US-20200097270 HGV Bequet, K Arfaoui
OPTIMIZED PARTITIONING OF MULTI-LAYER NETWORKS IN CORE-BASED NEUROSYNAPTIC ARCHITECTURES US US-20200097821 TK Nayak, A Amir
Processing with Compact Arithmetic Processing Element US US-20200097252 J Bates
Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models US US-20200082256-A1 K Hosokawa, M Ishii, S Kim, CH Lam, SC Lewis
Systems and methods for mapping matrix calculations to a matrix multiply accelerator US US-20200081937-A1 D Fick, M Henry, L Fick, M Parikh, S SKRZYNIARZ
MULTI-LEVEL IMAGE RECONSTRUCTION USING ONE OR MORE NEURAL NETWORKS US US-20200090383 S Dwivedi