power_consumption

Title company name (assignee) Country/Patent Coverage filing/creation date grant date id inventor/author priority date publication date representative figure link result link
Constraining function approximation hardware integrated with fixed-point to floating-point conversion US US-20200134475-A1 RA Hill, EW Mahurin, AD Lamb, A Danysh, E Plondke
DYNAMIC ADAPTATION OF DEEP NEURAL NETWORKS US US-20200134461 SM Chai, A Nadamuni Raghavan, S Parajuli
EDGE SERVER CPU WITH DYNAMIC DETERMINISTIC SCALING US US-20200125389 ST Palermo, N Gupta, V Srinivasan, C Macnamara
HARDWARE ARCHITECTURE AND PROCESSING UNITS FOR EXACT BAYESIAN INFERENCE WITH ON-LINE LEARNING AND METHODS FOR SAME US US-20200125979 AG Andreou, T Figliolia
RECURSIVE MULTI-FIDELITY BEHAVIOR PREDICTION US US-20200117958 KJ Brown, M Jain, AK Sadek
Optoelectronic Computing Systems US US-20200110992 A Hosseinzadeh, Y Xu, Y Bai, H Meng, R Gagnon, C Lu
EXPLOITING ACTIVATION SPARSITY IN DEEP NEURAL NETWORKS US US-20200104692 R Hill, A Lamb, M Goldfarb, A Ansari, C Lott
LOW SPIKE COUNT RING BUFFER MECHANISM ON NEUROMORPHIC HARDWARE US US-20200097801 A Andreopoulos
NEURAL PROCESSING UNIT (NPU) DIRECT MEMORY ACCESS (NDMA) MEMORY BANDWIDTH OPTIMIZATION US US-20200104691 J Bai, R Cammarota, M Goldfarb
NEURAL PROCESSING UNIT (NPU) DIRECT MEMORY ACCESS (NDMA) HARDWARE PRE-PROCESSING AND POST-PROCESSING US US-20200104690 J Bai, R Cammarota, M Goldfarb
OPTIMIZED PARTITIONING OF MULTI-LAYER NETWORKS IN CORE-BASED NEUROSYNAPTIC ARCHITECTURES US US-20200097821 TK Nayak, A Amir
Systems and methods for mapping matrix calculations to a matrix multiply accelerator US US-20200081937-A1 D Fick, M Henry, L Fick, M Parikh, S SKRZYNIARZ
COGNITIVE STORAGE DEVICE US US-20200082241 G Paillet, A Menendez
MULTI-LEVEL IMAGE RECONSTRUCTION USING ONE OR MORE NEURAL NETWORKS US US-20200090383 S Dwivedi